1. Field of the Invention
The present invention relates to the securing of integrated circuits, and in particular the protection of integrated circuits for chip cards against fraud.
The present invention more particularly relates to the securing of parallel signals processing circuits and particularly the securing of memory cells read circuits, in order to prevent fraudulent access to data stored in a memory.
2. Description of the Related Art
The memory cells read circuits, also called “sense amplifiers”, are particularly vulnerable to fraudsters' attacks aiming at discovering data in a memory. Indeed, when sense amplifiers read memory cells, the mere observation of their activity (observation of electrical potentials) makes it possible to determine the value of data stored in memory cells currently being read. When combined with an error injection into the addresses applied to the memory, this technique allows the value of data stored in protected areas of the memory to be deduced.
The memories present in the integrated circuits of chip cards are particularly subjects to this type of attack since they contain confidential data (secret keys, passwords . . . ) that fraudsters want to know.
To counter this type of attack, it is known to cipher the data contained in the memory. However, this solution increases the duration of data processing cycles because it requires ciphering the data before writing them in the memory and then deciphering the data read out of the memory before being able to exploit them.
It is also known to implant memory cells on a semi-conductor substrate without following the usual manufacturing rules of integrated circuits, so that memory cells of successive addresses are not physically neighbours but randomly arranged.
However, when a binary word is read out of a memory, several memory cells are simultaneously read, each memory cell containing one bit of the binary word. Each memory cell of determined rank supplies an electrical signal which is processed by a sense amplifier of determined rank. There thus exists a static relation between the rank of a memory cell within a group of cells containing a binary word and the rank of the sense amplifier allocated to the memory cell reading, thanks to which the bits supplied by the sense amplifiers are arranged in a determined order corresponding to their rank within the binary word. Thus, fraudsters can observe the activity of the sense amplifiers, deduce from it the value of data currently being read and then find the address of the memory cells containing these data. Consequently, a random arrangement of memory cells and a random address allocation to the memory cells do not allow fraud attempts to be efficiently countered and only allow the fraudster's work to be made more complex.